| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
3,893 |
11,440 |
34% |
|
| Number used as Flip Flops |
3,886 |
|
|
|
| Number used as Latches |
0 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
7 |
|
|
|
| Number of Slice LUTs |
4,174 |
5,720 |
72% |
|
| Number used as logic |
3,708 |
5,720 |
64% |
|
| Number using O6 output only |
2,648 |
|
|
|
| Number using O5 output only |
68 |
|
|
|
| Number using O5 and O6 |
992 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
265 |
1,440 |
18% |
|
| Number used as Dual Port RAM |
144 |
|
|
|
| Number using O6 output only |
4 |
|
|
|
| Number using O5 output only |
5 |
|
|
|
| Number using O5 and O6 |
135 |
|
|
|
| Number used as Single Port RAM |
4 |
|
|
|
| Number using O6 output only |
4 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
0 |
|
|
|
| Number used as Shift Register |
117 |
|
|
|
| Number using O6 output only |
38 |
|
|
|
| Number using O5 output only |
1 |
|
|
|
| Number using O5 and O6 |
78 |
|
|
|
| Number used exclusively as route-thrus |
201 |
|
|
|
| Number with same-slice register load |
190 |
|
|
|
| Number with same-slice carry load |
11 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
1,403 |
1,430 |
98% |
|
| Number of LUT Flip Flop pairs used |
4,761 |
|
|
|
| Number with an unused Flip Flop |
1,326 |
4,761 |
27% |
|
| Number with an unused LUT |
587 |
4,761 |
12% |
|
| Number of fully used LUT-FF pairs |
2,848 |
4,761 |
59% |
|
| Number of unique control sets |
350 |
|
|
|
Number of slice register sites lost
to control set restrictions |
1,476 |
11,440 |
12% |
|
| Number of bonded IOBs |
78 |
200 |
39% |
|
| Number of LOCed IOBs |
78 |
78 |
100% |
|
| IOB Flip Flops |
15 |
|
|
|
| Number of RAMB16BWERs |
16 |
32 |
50% |
|
| Number of RAMB8BWERs |
0 |
64 |
0% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2s |
1 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
| Number of BUFG/BUFGMUXs |
2 |
16 |
12% |
|
| Number used as BUFGs |
2 |
|
|
|
| Number used as BUFGMUX |
0 |
|
|
|
| Number of DCM/DCM_CLKGENs |
0 |
4 |
0% |
|
| Number of ILOGIC2/ISERDES2s |
7 |
200 |
3% |
|
| Number used as ILOGIC2s |
7 |
|
|
|
| Number used as ISERDES2s |
0 |
|
|
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
22 |
200 |
11% |
|
| Number used as IODELAY2s |
0 |
|
|
|
| Number used as IODRP2s |
0 |
|
|
|
| Number used as IODRP2_MCBs |
22 |
|
|
|
| Number of OLOGIC2/OSERDES2s |
51 |
200 |
25% |
|
| Number used as OLOGIC2s |
8 |
|
|
|
| Number used as OSERDES2s |
43 |
|
|
|
| Number of BSCANs |
1 |
4 |
25% |
|
| Number of BUFHs |
0 |
128 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
1 |
4 |
25% |
|
| Number of DSP48A1s |
3 |
16 |
18% |
|
| Number of ICAPs |
0 |
1 |
0% |
|
| Number of MCBs |
1 |
2 |
50% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
1 |
2 |
50% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
3.63 |
|
|
|